In this video, we will continue our survey of modern programmable logic devices
with small FPGAs from Xilinx including the Spartan 3AN and the Spartan 6.
We will use the Programmable Logic Device Selection Criteria we
established earlier to evaluate these devices.
As a reminder, there are 11 criteria.
Size or Logic Density, the amount of logic
in systems gates or LEs or Slices or ALMs.
Cost per logic gate, the Speed, their maximum clock frequency,
Power Consumption, both static and dynamic, Reprogrammability or
the configuration memory type, cost per I/O or I/O Density,
Hard IP available on chip, the memory, DSP, Blocks, Transceivers, etc.
Deterministic timing (timing is consistent in every implementation), Reliability,
measured by the FIT rate, Endurance, the number of programming cycles and
years of retention, and Design and Data Security.
Here's a portion of the Xilinx Spartan 3AN FPGA family data sheet.
The Spartan 3AN has reprogrammable flash configuration and user memory.
Note the equivalent gates up to 1.4 million.
25 K logic cells, considerably more logic than the CPLDs have.
This part is designed for low cost.
If you need more logic than this,
then you need to select the larger part that will meet your requirements.
We'll talk about larger parts as we continue in this module.
The speed is limited to 350 megahertz on global
clock buffers, which is faster than CPLDs.
Maximum power draw is between 20 and 200 milliamps depending on part size.
This device has up to 502 I/O pins, a 50 to 1 ratio of logic cells to I/O.
There are 23 supported I/O standards.
20 years data retention is good, as is 100,000 programming cycles endurance.
Design security is enhanced by the integration of the configuration
memory on a single chip.
Hard IP blocks have been added including RAM blocks,
multipliers, and Digital Clock Managers.
Initially, programmable logic devices specify most information in
the data sheet.
However, now not all the information is found in the data sheet.
Some is found in the corresponding user's guide or handbook.
Here is the overall architecture of the Spartan 3.
I/O is on the outside and includes logic blocks,
RAM, multipliers and clock manager.
Here is a picture of a Spartan 3 slice, one-half of a logic block.
The heart of the slice is 2 4-input LUTs and 2 flip-flop outputs.
It also has some carry chain logic for creating adders and
shift clock generation to make shift registers.
This is a simplified picture of the LUT resources in a slice.
The LUTs can also be used as distributed memory.
Each LUT is 16-bits of RAM, or has a 16-bit shift register.
Here is a portion of the Xilinx Spartan 6 FPGA family data sheet.
The Spartan 6 has reprogrammable SRAM configuration,
which requires an external nonvolatile memory,
usually a flash memory, to load the configuration at power up.
The delay before the device becomes active is several milliseconds.
Note it has up to a 147 K logic cells, considerably more logic.
This part is designed for low cost.
Additional Hard IP blocks are included, including 180 DSP slices,
almost 5,000 kilobytes of Block RAM, and
up to 8 High-Speed Transceivers.
This device has up to 540 I/O pins, a 300 to 1 ratio of logic cells to I/O.
There are 55 supported I/O standards.
Speed is limited to 400 megahertz on global clock buffers
which is faster than CPLDs.
Maximum static power draw is between 20 and 51 milliamps depending on part size.
Dynamic power is not specified.
Other information is found in several user's guides.
Here is a picture of a Spartan 6 slice, one-quarter of a logic block.
The heart of the slice is 4 6-input LUTs and 8 flip-flops.
It also has some carry chain logic for creating adders.
There are three types of slices with varying capabilities.
As you can see, the logic is becoming more and more complex.
This is a simplified picture of the LUT resources in the slice.
The LUTs can also be used as distributed memory.
Each slice can create up to a 256 by 1 RAM or
ROM or as a 32-bit shift register per slice.
Recall, the 4-bit comparator.
How many comparator bits can be implemented in a LUT?
In the 3AN case there are only 4-inputs, so only a 2-bit comparator can be created.
Larger comparators require that the LUTs be cascaded.
Although the logic is efficiently used,
there is an added delay relative to the CPLD implementation.
In the Spartan 6 case, the 6-input LUT will handle 3-bits of comparators,
so wider comparators can be made with less delay.
How many full adders can be made in a logic cell?
For a Spartan 3AN at first blush, it would seem to require 2 LUTs per 1 adder.
The logic on the left can be implemented in 2 LUTs with
3-inputs each to generate the sum and the carry.
The problem with this implementation, that it requires 2 LUT for every input bit,
and the carry propagates through the full LUT delay for each bit.
A better implementation is to use look ahead and determine if the input carry
signal needs to be propagated where the inputs are different, or
generated when both inputs are high.
This is shown on the left.
To optimize the implementation of this logic, the Spartan-3 Generation CLB
provides a dedicated XOR gate outside the LUT, to generate the sum called
the XORCY and a dedicated MUX to provide the carry called the MUXCY.
In this way, each LUT can implement 1 full adder bit.
This structure makes more efficient use of logic resources
than what was seen in the CPLDs.
This is also true of shift registers,
which can be implemented entirely using the LUT, 16-bits per LUT for
a Spartan 3AN, 32-bits per slice for the Spartan 6.
In this video, we have learned Xilinx offers several smaller FPGA families,
including the Spartan 3AN and Spartan 6, which are both currently available.
The Spartan 3AN uses a on-chip FLASH configuration memory,
so it is a single-chip solution.
The Spartan 6 uses SRAM configuration memory, so
it needs an additional nonvolatile memory device to hold the configuration.
The Spartan 3AN has a logic cell based on a 4-input LUT and a flip-flop,
with additional logic to help efficiently create adders and shift registers.
The Spartan 6 has a 6-input LUT with 2 flip-flops per logic cell.
Xilinx small FPGAs are more efficient in implementation of adders or
shift registers than CPLDs.
Xilinx small FPGAs include additional Hard IP blocks, including Multipliers and
DSP, RAM blocks, Clock generation, and High-Speed Transceivers.
Timothy ScherrSenior Instructor and Professor of Engineering Practice
