C?d: e; What does this do? Well, it loads a.

If, if, if c is true, it loads a with d, if c is false, it loads a with e.

Well, you can think about actually doing this with, some sort of If-then-else,

piece a code. Which is pretty common.

If a < b So you can sort of put, that here.

X gets a versus x getting b. That's our select operator.

Well we add two, two special instructions here for our limited predication.

Move if zero and move if not zero. Well, what does this do?

Well if this operand is equal to zero, then this rd gets rs, else that's all it

does. That's all that instruction does.

And the flip one here is, it checks if it's not equal to zero.

Why is this cool? Well, this allows us to transform control

flow into a data instruction. So, we've taken a branch out, so if we

look at this piece of code, if we're doing it with branches set less than, we do a

branch. So, this, this computes our condition

co-flag here, branch equals and if it's, the one way a branch is here, if not, it

jumps over it. So, we have a bunch of control flow here.

We have two control flow operations, the branch and the jump.

When we add these instructions, we can basically do that if then else in, in an

instruction. And, basically every VILW processor you're

going to look at is going to have predication, or at least limited

predication. This is, this is not full predication,

this is limited predication. We'll talk about full predication in a

second. Okay so that, let's, let's think about

that for a second. We just took control flow.

We turned it into something which is never going to take a branch mispredict.

That sounds pretty cool cuz branch mispredicts, you know, were pretty, pretty

bad. If we had a branch which was harder to

predict, we didn't know with high probability if a was greater than b or

not. We can just sort of stick this code

sequence in here and just be done with it. And why it's really important for very

long instructional processors, is because whenever you take a branch and mis

predict, you basically have a bunch of dead instructions.

And you can't schedule something in, in that point.

But the, a, an Out-of-Order Superscalar can attempt to sort of schedule things in

there. We can try to schedule non-dependent

operations. But our compiler has to come up with some

code sequence, and has to make them parallel at compile time.