And you need to hold the bus the whole time while you do the arbitration
control, address data and data come back.
And it could be a long time, because main
memory can take a long time to return data.
And, and this, this is a problem, so what did people think about doing?
Well, they applied ideas from processor design and
said, maybe we can try to pipeline the bus.
So note, and let's flip back and forth here for a second.
The title of the slide changes, but the content, the content doesn't.
So this pipeline bus actually looks the same.
So it has the same data, but now instead of arbitrating and winning
the entire bus, and holding the entire bus for a long period of time.
Instead, we subdivide all these different categories and actually pipeline
the access to them and use them only when they're needed.
So, we can actually take a look at this as a picture here.
And we can see, for instance, on a pipelined bus, you
might first let's say processor 1 is trying to do something.
It'll assert processor 1 onto the arbitration lines and let's say it wins.