Logic-Level Timing: Computing ATs, RATs, Slacks, and Worst Paths

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From the course by University of Illinois at Urbana-Champaign
VLSI CAD Part II: Layout
11 ratings
University of Illinois at Urbana-Champaign

VLSI CAD Part II: Layout

11 ratings
From the lesson
Timing Analysis

Meet the Instructors

  • Rob A. Rutenbar
    Rob A. Rutenbar
    Adjunct Professor
    Department of Computer Science