Об этом курсе
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Промежуточный уровень

This course is aimed at students with prior programming experience and a desire to understand computation approaches to problem solving.

Прибл. 12 часа на выполнение

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Английский

Субтитры: Английский

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Programming PrinciplesComputer ArchitectureProgramming Language Concepts

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Гибкие сроки

Назначьте сроки сдачи в соответствии со своим графиком.

Промежуточный уровень

This course is aimed at students with prior programming experience and a desire to understand computation approaches to problem solving.

Прибл. 12 часа на выполнение

Предполагаемая нагрузка: 4-10 hours/week...

Английский

Субтитры: Английский

Программа курса: что вы изучите

Неделя
1
2 ч. на завершение

Familizarize youself with FPGA technologies

From the mid-1980s, reconfigurable computing has become a popular field due to the FPGA technology progress. An FPGA is a semiconductor device containing programmable logic components and programmable interconnects but no instruction fetch at run time, that is, FPGAs do not have a program counter. In most FPGAs, the logic components can be programmed to duplicate the functionality of basic logic gates or functional Intellectual Properties (IPs). FPGAs also include memory elements composed of simple flip-flops or more complex blocks of memories. Hence, FPGA has made possible the dynamic execution and configuration of both hardware and software on a single chip. This module provides a detailed description of FPGA technologies starting from a general description down to the discussion on the low-level configuration details of these devices, to the bitstream composition and the description of the configuration registers.

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9 видео ((всего 57 мин.)), 2 тестов
9 видео
FPGA-based systems and reconfiguration4мин
Programmable System-on-Multiple Chips7мин
Programmable System-on-Chips4мин
FPGAs main building blocks7мин
How to program an FPGA: bitstream and configuration5мин
How to program an FPGA: system description and physical design7мин
CAD Tools for FPGA-based systems design6мин
An introuction to the SDx development environment9мин
2 практического упражнения
QUIZ 140мин
QUIZ 230мин
Неделя
2
3 ч. на завершение

A bird's eye view on SDAccel

The Xilinx SDAccel Development Environment let the user express kernels in OpenCL C, C++ and RTL (as an example we can think of, SystemVerilog, Verilog or VHDL) to run on Xilinx programmable platforms. The programmable platform is composed of (1) the SDAccel Xilinx Open Code Compiler (XOCC), (2) a Device Support Archive (DSA) which describes the hardware platform, (3) a software platform, (4) an accelerator board, and5. last but not least, the SDAccel OpenCL runtime. Within this module, after an introduction to OpenCL, we are going to see how this language has been sued in SDAccel and the main "components" of this toolchain.

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7 видео ((всего 37 мин.)), 1 материал для самостоятельного изучения, 1 тест
7 видео
An introduction to SDAccel and the OpenCL-based flow5мин
OpenCL computational model: global and local sizes4мин
Not only OpenCL! The Rationale behind the RTL and C flows5мин
SDAccel memory model5мин
SDAccel "emulations"5мин
SDAccel runtime4мин
1 материал для самостоятельного изучения
SDAccel Environment Programmers Guide
1 практическое упражнение
QUIZ 330мин
Неделя
3
3 ч. на завершение

On how to optmize your system

Within this module, Before getting into the optimisation, we will first understand how an FPGA is working, also from a computational point of view. Although the traditional FPGA design flow is more similar to a regular IC than a processor, an FPGA provides significant cost advantages in comparison to an IC development effort and offers the same level of performance in most cases. Another advantage of the FPGA when compared to the IC is its ability to be dynamically reconfigured. This process, which is the same as loading a program in a processor, can affect part or all of the resources available in the FPGA fabric. When compared with processor architectures, the structures that comprise the FPGA fabric enable a high degree of parallelism in application execution. The custom processing architecture generated by SDAccel for an OpenCL kernel presents a different execution paradigm. This must be taken into account when deciding to port an application from a processor to an FPGA. To better understand such a scenario we will briefly compare a processor sequential execution with the intrinsic parallel nature of an FPGA implementation. Furthermore, within this module we are going to familiarise ourselves with the application optimisation flow.The Xilinx SDAccel Environment is a complete Software Development Environment, for creating, compiling, and optimising OpenCL applications with the objective of being accelerated on Xilinx FPGAs. From a designer perspective we can organise the flow for optimising an application in the SDAccel Environment as a three phases flow. Those three phases are: (1) baselining functionalities and performance, (2) optimising data movement and (3) optimising kernel computation

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5 видео ((всего 37 мин.)), 1 материал для самостоятельного изучения, 1 тест
5 видео
FPGA Parallelism vs Processor Architecture 1/27мин
FPGA Parallelism vs Processor Architecture 2/28мин
Scheduling, Pipelining, and Dataflow8мин
Application Optimization Flow6мин
1 материал для самостоятельного изучения
SDAccel Environment Profiling and Optimisation Guide1ч 30мин
1 практическое упражнение
QUIZ 430мин
5 ч. на завершение

Optimize your system via SDAccel

In this module we will provide a bird's eye view on the available SDAccel optimisations. The presented optimisations are not the only available ones, but they are more a list of recommendations to optimise the performance of an OpenCL application that have to be used as a starting point for ideas to consider or investigate further. Within this context we will organise these “recommendations” in three sets of optimisations: (1) arithmetic optimisations, (2) data-related optimisations, and finally (3) memory-related optimisations.

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6 видео ((всего 34 мин.)), 2 материалов для самостоятельного изучения, 1 тест
6 видео
Interface optimizations: Overall context and an overview of a typical target architecture6мин
Interface optimizations: a first example5мин
Burst data transfer3мин
Using full AXI data width4мин
Using multiple memory banks3мин
2 материала для самостоятельного изучения
SDAccel Environment Profiling and Optimisation Guide
Sources Codes1ч 30мин
1 практическое упражнение
QUIZ 530мин
Неделя
4
4 ч. на завершение

Other optimizations

After an overall description of possibile optimisations, within this module we will focus on four specific optimisations (1) loop unrolling, (2) loop pipelining, (3) array partitioning and (4) the host optimisations. First, we will describe loop unrolling which means to unroll the loop iterations so that, the number of iterations of the loop reduces, and the loop body performs extra computation. This technique allows to expose additional instruction level parallelism that Vivado HLS can exploit to implement the final hardware design. After that we will present the loop pipelining optimisation, where we will move from a sequential execution of the loop iterations to a pipelined execution in which the loop iterations are overlapped in time. After that we will present the array partitioning optimisation which allows to optimise the usage of BRAM resources in order to improve the performance of the kernel. Finally, at the end of this module we are going to discuss optimisations related to the host system that is responsible for transferring the data to and from the FPGA board, as well as to send the command to start the execution of a kernel.

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6 видео ((всего 43 мин.)), 2 материалов для самостоятельного изучения, 1 тест
6 видео
Kernel optimization: loop unrolling 2/26мин
Kernel optimization: loop pipelining9мин
Kernel optimization: array partitioning 1/28мин
Kernel optimization: array partitioning 2/27мин
Host optimizations5мин
2 материала для самостоятельного изучения
SDAccel Environment Profiling and Optimisation Guide1ч 30мин
Source Codes1ч 30мин
1 практическое упражнение
QUIZ 630мин
3 ч. на завершение

An introduction to FPGA-augmented cloud infrastructures

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3 видео ((всего 14 мин.)), 1 материал для самостоятельного изучения, 1 тест
3 видео
An introduction to SDAccel and the AWS EC2 F1 instances8мин
Closing remarks and future directions1мин
1 материал для самостоятельного изучения
A Scalable FPGA Design for Cloud N-Body Simulation
1 практическое упражнение
QUIZ 720мин

Преподаватели

Avatar

Marco Domenico Santambrogio

Associate Professor
DEIB - Dept. of Electronics, Information and Bioengineering

О Politecnico di Milano

Politecnico di Milano is a scientific-technological University, which trains engineers, architects and industrial designers. From 2014 Politecnico di Milano started the release of several MOOCs, developed by the service for digital learning METID (Methods and Innovative Technologies for Learning), giving everybody the chance to enhance personal skills....

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