This course can also be taken for academic credit as ECEA 5361, part of CU Boulder’s Master of Science in Electrical Engineering degree.
Этот курс входит в специализацию ''Специализация FPGA Design for Embedded Systems'
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Специализация FPGA Design for Embedded SystemsКолорадский университет в БоулдереОб этом курсе
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Курс 2 из 4 в программе
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Средний уровень
Прибл. 36 часов на выполнение
Английский
Субтитры: Арабский, Французский, Португальский (Европа), Китайский (упрощенное письмо), Итальянский, Вьетнамский, Корейский, Немецкий, Русский, Турецкий, Английский, Испанский
Приобретаемые навыки
Writing Code in VerilogSimulating FPGA DesignsDesigning FPGA LogicDesigning Test BenchesWriting code in VHDL
Сертификат, ссылками на который можно делиться с другими людьми
Получите сертификат по завершении
100% онлайн
Начните сейчас и учитесь по собственному графику.
Курс 2 из 4 в программе
Гибкие сроки
Назначьте сроки сдачи в соответствии со своим графиком.
Средний уровень
Прибл. 36 часов на выполнение
Английский
Субтитры: Арабский, Французский, Португальский (Европа), Китайский (упрощенное письмо), Итальянский, Вьетнамский, Корейский, Немецкий, Русский, Турецкий, Английский, Испанский
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Колорадский университет в Боулдере
CU-Boulder is a dynamic community of scholars and learners on one of the most spectacular college campuses in the country. As one of 34 U.S. public institutions in the prestigious Association of American Universities (AAU), we have a proud tradition of academic excellence, with five Nobel laureates and more than 50 members of prestigious academic academies.
Сделайте шаг навстречу диплому магистра.
курс входит в онлайн-программу ''Master of Science in Electrical Engineering' от партнера Колорадский университет в Боулдере.
Если вы переходите на полную программу, курсы засчитываются при получении диплома.
Программа курса: что вы изучите
8 ч. на завершение
Basics of VHDL
This module introduces the basics of the VHDL language for logic design. It describes the use of VHDL as a design entry method for logic design in FPGAs and ASICs. To provide context, it shows where VHDL is used in the FPGA design flow. Then a simple example, a 4-bit comparator, is used as a first phrase in the language. VHDL rules and syntax are explained, along with statements, identifiers and keywords. Finally, use of simulation as a means of testing VHDL circuit designs is demonstrated using ModelSim, a simulator software tool. Programming assignments are used to develop skills and reinforce the concepts presented.
8 ч. на завершение
10 видео ((всего 48 мин.)), 3 материалов для самостоятельного изучения, 6 тестов
10 видео
Why Learn VHDL?1мин
FPGA Design Flow3мин
Intro to VHDL: Finite State Machine3мин
How to speak VHDL, first phrases6мин
VHDL Assignments, Operators, Types3мин
VHDL Rules and Syntax, Interface Ports3мин
VHDL in ModelSim: Download and Install3мин
VHDL in ModelSim: Adding to your Toolkit6мин
Submitting VHDL Programming Assignments11мин
3 материала для самостоятельного изучения
Hardware Description Languages for FPGA Design Assessment Strategy10мин
Misson 2-001: Week 1 Readings2ч
Files for Week 1 Programming Assignments10мин
2 практических упражнения
VHDL Find the Code Errors30мин
Module 1 Quiz30мин
12 ч. на завершение
VHDL Logic Design Techniques
In this module use of the VHDL language to perform logic design is explored further. Many examples of combinatorial and synchronous logic circuits are presented and explained, including flip-flops, counters, registers, memories, tri-state buffers and finite state machines. Methods of hierarchical design and modular design techniques are explained and demonstrated. How to create test benches is described as a means for design verification. Students are giving ample opportunity to practice and refined their design technique using the programming assignments.
12 ч. на завершение
10 видео ((всего 52 мин.)), 2 материалов для самостоятельного изучения, 6 тестов
10 видео
Combinatorial Circuits4мин
Synchronous Logic: Latches and Flip Flops4мин
Synchronous Logic: Counters and Registers6мин
Buses and Tristate Buffers3мин
Modular Designs: Components, Generate and Loops in VHDL3мин
Test Benches in VHDL: Combinatorial8мин
Test Benches in VHDL: Synchronous5мин
Memory in VHDL7мин
Finite State Machines in VHDL8мин
2 материала для самостоятельного изучения
Week 2 Readings2ч
Files for Week 2 Programming Assignments10мин
1 практическое упражнение
Module 2 Quiz30мин
7 ч. на завершение
Basics of Verilog
This module introduces the basics of the Verilog language for logic design. It describes the use of Verilog as a design entry method for logic design in FPGAs and ASICs, including the history of Verilog's development. Then a simple example, a 4-bit comparator, is used as a first phrase in the language. Verilog rules and syntax are explained, along with statements, operators and keywords. Finally, use of simulation as a means of testing Verilog circuit designs is demonstrated using ModelSim, a simulator tool. Programming assignments are used to develop skills and reinforce the concepts presented.
7 ч. на завершение
9 видео ((всего 92 мин.)), 2 материалов для самостоятельного изучения, 6 тестов
9 видео
Your First Verilog phrase11мин
Verilog Rules and Syntax; Keywords and Identifiers; Sigasi/Quartus editing12мин
Verilog Statements and Operators16мин
Verilog Modules, Port Modes and Data Types10мин
Verilog Structure10мин
Testing with ModelSim5мин
Verilog Evaluation11мин
Submitting Verilog Programming Assignments10мин
2 материала для самостоятельного изучения
Week 3 Readings1ч 10мин
Files for Week 3 Programming Assignments10мин
2 практических упражнения
Verilog Find the Errors20мин
Module 3 Quiz30мин
10 ч. на завершение
Verilog and System Verilog Design Techniques
In this module use of the Verilog language to perform logic design is explored further. Many examples of combinatorial and synchronous logic circuits are presented and explained, including flip-flops, counters, registers, memories, tri-state buffers and finite state machines. Methods of hierarchical design and modular design techniques are explained and demonstrated. How to create test benches is described as a means for design verification. Students are giving ample opportunity to practice and refined their design technique by writing code as required by the programming assignments.
10 ч. на завершение
10 видео ((всего 48 мин.)), 2 материалов для самостоятельного изучения, 6 тестов
10 видео
Combinatorial Circuits5мин
Synchronous Logic: Latches and Flip Flops3мин
Synchronous Logic: Counters and Registers5мин
Buses and Tristate Buffers3мин
Modular Design in Verilog3мин
Testbenches in Verilog7мин
Testbenches in Verilog II2мин
Memory with Verilog4мин
Verilog Finite State Machines7мин
2 материала для самостоятельного изучения
Week 4 Readings15мин
Files for Week 4 Programming Assignments10мин
1 практическое упражнение
Module 4 Quiz30мин
Рецензии
Лучшие отзывы о курсе HARDWARE DESCRIPTION LANGUAGES FOR FPGA DESIGN
от партнера MS15 мая 2020 г.
This course is very helpful in understanding the basics of hardware description languages and now after doing this course i am very much comfortable in using verilog and vhdl language.
от партнера RL1 мая 2020 г.
The Verilog course was very good. However the vhdl course could have been better.Needed a bit more clarity on the assignments.The lectures could have used a bit more explanation.
от партнера KK4 июня 2020 г.
This is very good course , but i found some little missing details related to reading materials . But this was really very helpful course for me as fresher .
от партнера JP6 окт. 2020 г.
I think this is a good start in learning how to write VHDL and Verilog. I would like to see a next level course or recommendations for further writing code.
Специализация FPGA Design for Embedded Systems: общие сведения
The objective of this course is to acquire proficiency with Field Programmable Gate Arrays (FPGA)s for the purpose of creating prototypes or products for a variety of applications. Although FPGA design can be a complex topic, we will introduce it so that, with a little bit of effort, the basic concepts will be easily learned, while also providing a challenge for the more experienced designer. We will explore complexities, capabilities and trends of Field Programmable Gate Arrays (FPGA) and Complex Programmable Logic Devices (CPLD). Conception, design, implementation, and debugging skills will be practiced. We will learn specifics around embedded IP and processor cores, including tradeoffs between implementing versus acquiring IP. Projects will involve the latest software and FPGA development tools and hardware platforms to help develop a broad perspective of the capabilities of various Programmable SoC solutions. Topics include:
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