This course can also be taken for academic credit as ECEA 5361, part of CU Boulder’s Master of Science in Electrical Engineering degree.
Этот курс входит в специализацию ''Специализация FPGA Design for Embedded Systems'
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Специализация FPGA Design for Embedded SystemsКолорадский университет в БоулдереОб этом курсе
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100% онлайн
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Курс 2 из 4 в программе
Средний уровень
Прибл. 36 часов на выполнение
Английский
Субтитры: Арабский, Французский, Португальский (Европа), Итальянский, Вьетнамский, Немецкий, Русский, Английский, Испанский
Приобретаемые навыки
- Writing Code in Verilog
- Simulating FPGA Designs
- Designing FPGA Logic
- Designing Test Benches
- Writing code in VHDL
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Сертификат, ссылками на который можно делиться с другими людьми
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100% онлайн
Начните сейчас и учитесь по собственному графику.
Курс 2 из 4 в программе
Средний уровень
Прибл. 36 часов на выполнение
Английский
Субтитры: Арабский, Французский, Португальский (Европа), Итальянский, Вьетнамский, Немецкий, Русский, Английский, Испанский
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Колорадский университет в Боулдере
CU-Boulder is a dynamic community of scholars and learners on one of the most spectacular college campuses in the country. As one of 34 U.S. public institutions in the prestigious Association of American Universities (AAU), we have a proud tradition of academic excellence, with five Nobel laureates and more than 50 members of prestigious academic academies.
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курс входит в онлайн-программу ''Master of Science in Electrical Engineering' от партнера Колорадский университет в Боулдере.
Если вы переходите на полную программу, курсы засчитываются при получении диплома.
Программа курса: что вы изучите
8 ч. на завершение
Basics of VHDL
This module introduces the basics of the VHDL language for logic design. It describes the use of VHDL as a design entry method for logic design in FPGAs and ASICs. To provide context, it shows where VHDL is used in the FPGA design flow. Then a simple example, a 4-bit comparator, is used as a first phrase in the language. VHDL rules and syntax are explained, along with statements, identifiers and keywords. Finally, use of simulation as a means of testing VHDL circuit designs is demonstrated using ModelSim, a simulator software tool. Programming assignments are used to develop skills and reinforce the concepts presented.
8 ч. на завершение
10 видео ((всего 48 мин.)), 3 материалов для самостоятельного изучения, 6 тестов
12 ч. на завершение
VHDL Logic Design Techniques
In this module use of the VHDL language to perform logic design is explored further. Many examples of combinatorial and synchronous logic circuits are presented and explained, including flip-flops, counters, registers, memories, tri-state buffers and finite state machines. Methods of hierarchical design and modular design techniques are explained and demonstrated. How to create test benches is described as a means for design verification. Students are giving ample opportunity to practice and refined their design technique using the programming assignments.
12 ч. на завершение
10 видео ((всего 52 мин.)), 2 материалов для самостоятельного изучения, 6 тестов
7 ч. на завершение
Basics of Verilog
This module introduces the basics of the Verilog language for logic design. It describes the use of Verilog as a design entry method for logic design in FPGAs and ASICs, including the history of Verilog's development. Then a simple example, a 4-bit comparator, is used as a first phrase in the language. Verilog rules and syntax are explained, along with statements, operators and keywords. Finally, use of simulation as a means of testing Verilog circuit designs is demonstrated using ModelSim, a simulator tool. Programming assignments are used to develop skills and reinforce the concepts presented.
7 ч. на завершение
9 видео ((всего 92 мин.)), 2 материалов для самостоятельного изучения, 6 тестов
10 ч. на завершение
Verilog and System Verilog Design Techniques
In this module use of the Verilog language to perform logic design is explored further. Many examples of combinatorial and synchronous logic circuits are presented and explained, including flip-flops, counters, registers, memories, tri-state buffers and finite state machines. Methods of hierarchical design and modular design techniques are explained and demonstrated. How to create test benches is described as a means for design verification. Students are giving ample opportunity to practice and refined their design technique by writing code as required by the programming assignments.
10 ч. на завершение
10 видео ((всего 48 мин.)), 2 материалов для самостоятельного изучения, 6 тестов
Рецензии
Лучшие отзывы о курсе HARDWARE DESCRIPTION LANGUAGES FOR FPGA DESIGN
от партнера MS15 мая 2020 г.
This course is very helpful in understanding the basics of hardware description languages and now after doing this course i am very much comfortable in using verilog and vhdl language.
от партнера RL1 мая 2020 г.
The Verilog course was very good. However the vhdl course could have been better.Needed a bit more clarity on the assignments.The lectures could have used a bit more explanation.
от партнера JS6 июня 2021 г.
I really liked this course . if someone wants to know how digital circuits are made inside of computer then this course could be proven as turning point in his way of learning .
от партнера MB23 июня 2021 г.
Good VHDL intro, Verilog was kind of light, especially the reference material. Free Range VHDL was a great reference. The Verilog section needs something similar.
Специализация FPGA Design for Embedded Systems: общие сведения
The objective of this course is to acquire proficiency with Field Programmable Gate Arrays (FPGA)s for the purpose of creating prototypes or products for a variety of applications. Although FPGA design can be a complex topic, we will introduce it so that, with a little bit of effort, the basic concepts will be easily learned, while also providing a challenge for the more experienced designer. We will explore complexities, capabilities and trends of Field Programmable Gate Arrays (FPGA) and Complex Programmable Logic Devices (CPLD). Conception, design, implementation, and debugging skills will be practiced. We will learn specifics around embedded IP and processor cores, including tradeoffs between implementing versus acquiring IP. Projects will involve the latest software and FPGA development tools and hardware platforms to help develop a broad perspective of the capabilities of various Programmable SoC solutions. Topics include:
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